Department
Image Display Technology Lab
Job Description
1. Responsible for FPGA control scheme design of video processing system and FPGA control circuit design;
2. Edit FPGA control code and debugging system program;
3. Follow the code specification, complete the assigned development tasks and ensure the development progress of the project;
4. Maintenance relevant products and optimize code, responsible for new technology research;
5. Responsible for writing and organizing technical documentation during the development process.
Qualifications
1. Major in communication, electronic engineering or related fields, engage in FPGA development work for more than 2 years, with video processing or communication industry experience;
2. Proficient in Verilog, familiar with the FPGA development process of ALTERA/XILINX/LATTICE platform, and proficient in the use of Quartus, ISE, Modelsim and other development tools;
3. Familiar with R&D project process, familiar with hardware circuit design knowledge and schematic design tools, proficient in using hardware debugging instruments.
Location
9-10F, High-Tech Zone Union Tower, No.63, Xuefu Road, Nanshan District, Shenzhen, Guangdong, China
